arinc inputs test inputs outputs v (a) - v (b) test a test b out a out b null 0 0 0 0 zero 0 0 0 1 one 0 0 1 0 don't care 0 1 0 1 don't care 1 0 1 0 don't care 1 1 0 0 general description the hi-8482 bus interface unit is a silicon gate cmos de- vice designed as a dual differential line receiver in accor- dance with the requirements of the arinc 429 bus speci- fication. the device translates incoming arinc 429 sig- nals to normal cmos/ttl levels on each of its two inde- pendent receive channels. the hi-8482 is also function- ally equivalent to the fairchild/raytheon rm3183. the self-test inputs force the outputs to either a zero, one, or null state for system tests. while in self-test mode, the arinc inputs are ignored. all the arinc inputs have built-in hysteresis to reject noise that may be present on the arinc bus. additional input noise filtering can also be accomplished with exter- nal capacitors. the hi-8482 line receiver is one of several options of- fered by holt integrated circuits to interface to the arinc bus. the digital data processing for serial-to-parallel con- version and clock recovery can be accomplished with the hi-6010, hi-8683 or similar devices. the hi-8482 is available in a variety of ceramic & plastic packages including small outline (soic), dip & leadless chip carrier (lcc). j-lead plcc, cerquad, features converts arinc 429 levels to digital data direct replacement for the rm3183 greater than 2 volt receiving hysteresis ttl and cmos outputs and test inputs military screening available 20-pin soic, plcc, cerquad, dip & lcc packages are available pin configurations (top views) truth table 3 - cap2b 2 - testa 1--v 20 - testb 19 - cap1a s hi-8482j hi-8482jt 20 - pin plastic j-lead plcc 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 +v - 11 out1b - 12 n/c-13 l s march 2007 hi-8482psi hi-8482pst 20 - pin plastic small outline (soic) - wb 20 - testb 19 - cap1a 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 13 - n/c 12 - out1b 11-+v s -v - 1 testa - 2 cap2b - 3 in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 s l (see page 6 for additional package pin configurations) (ds8482 rev. g) 03/07 hi-8482 arinc 429 dual line receiver holt integrated circuits www.holtic.com
functional description the hi-8482 contains two independent arinc 429 receive channels. the diagram in figure 1 illustrates a typical hi- 8482 receive channel. the differential arinc signal input is converted to a positive signal referenced to ground through level shifters and a unity gain differential amplifier. a positive differential input signal is converted to a positive signal on the plus output of the differential amplifier. this output is proportional in amplitude to the original input signal. at the same time, the corresponding minus output is pulled to gnd. likewise when a negative input signal is present at the arinc inputs, a positive signal is present on the minus output and the plus output is pulled to gnd. the outputs of the differential amplifier are compared with the one, zero and null threshold levels to produce the appropriate logic level on the outa and outb outputs of the device. the arinc clock signal may be recovered through a nor function of outa and outb. the test inputs logically disconnect the outputs of the comparators from outa and outb and force the device outputs to one of the three valid states (figure 5). this alleviates having to ground the arinc inputs during test mode operation. arinc levels the arinc 429 specification requires the following detection levels: one +6.5v to +13v null +2.5v to -2.5v zero -6.5v to -13v the hi-8482 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 5v for the worst case condition. state differential voltage noise the input hysteresis is set to reject voltage level transi- tions in the undefined region between the maximum zero level and the minimum null level and the unde- fined region between the maximum null level and the minimum one level. therefore, once a valid input differential voltage threshold is detected, the outputs will remain at a valid logic state until a new valid input voltage is detected. in addition to the hysteresis, the capa and capb pins make it possible to add simple rc filters to the arinc inputs. hi-8482 figure 1 - block diagram typical channel diff amp outa outb plus minus testa testb ina capa inb capb comp +vs +v l level shift level shift -vs gnd comparators w / hysteresis comp detect level detect level holt integrated circuits 2
typical applications applications the standard connections for the hi-8482 are shown in figure 2. decoupling of the supply should be done near the ic to avoid propagation of noise spikes due to switching transients. the ground (gnd) connection should be sturdy and isolated from large switching currents to provide a quiet ground reference. the hi-8482 can be used with hi-3182 or hi-8585 line drivers to provide a complete analog arinc 429 interface solution. a simple application, which can be used in systems requiring a repeater type circuit for long transmissions or for test interfaces, is given in figure 3. more hi-3182 or hi-8585 drivers may be added to test multiple arinc channels, as shown. figure 2 - arinc receiver standard connections +5v +15v hi-8482 arinc channel 2 logic test inputs n/c n/c out2a out1a out1b a b a b 39 pf 39 pf 39 pf 39 pf in1a in1b cap1a cap1b in2a in2b cap2a cap2b testa testb arinc channel 1 channel 1 data out to logic channel 2 data out to logic -15v figure 3 - arinc repeater circuit arinc output channel 1 arinc output channel 2 arinc input channel data (a) data (b) data (a) data (b) out1a out1b in1a in1b aout bout aout bout hi-3182 or hi-8585 to additional channels a b a b hi-3182 or hi-8585 1/2 hi-8482 out2b hi-8482 holt integrated circuits 3
figure 5 testa testb +5v 0v +5v 0v t tlh t thl t tlh t r t thl t f 90% 10% 50% 50% outa (test) outb (test) 90% figure 4 arinc differential input +10v 0v -10v outa outb t plh t phl t plh t r t phl t f 10% 50% 50% timing diagrams symbol function description in2b input arinc input terminal b of channel 2 out1a output ttl output terminal a of channel 1 out1b output ttl output terminal b of channel 1 out2a output ttl output terminal a of channel 2 out2b output ttl output terminal b of channel 2 testa input test input terminal a testb input test input terminal b +v power +5 volts 10% +vs power +12 volts 10% or +15 volts 10% -vs power -12 volts 10% or -15 volts 10% l cap1a input filter capacitor input for terminal a of channel 1 cap1b input filter capacitor input for terminal b of channel 1 cap2a input filter capacitor input for terminal a of channel 2 cap2b input filter capacitor input for terminal b of channel 2 gnd power 0 volts in1a input arinc input terminal a of channel 1 in1b input arinc input terminal b of channel 1 in2a input arinc input terminal a of channel 2 symbol function description pin description table hi-8482 holt integrated circuits 4
hi-8482 note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings electrical characteristics voltage at arinc inputs: .......................................................-29v to +29v voltage at any other input:.............................................-0.3v to v + 0.3v output short circuit protected: .............................................not protected storage temperature range: .........................................-65c to +150c soldering temperature: (ceramic).................................30 sec. at +300c (plastic - leads)........................10 sec. at +280c (plastic - body) ................................+220c max. l supply voltage, +v :......................................................................+20 vdc -v : .......................................................................-20 vdc +v :........................................................................+7 vdc operating temperature range: (industrial) .........................-40c to +85c (hi-temp) ........................-55c to +125c (military) ..........................-55c to +125c internal power dissipation: ..............................................................900mw s s l (voltages referenced to gnd = 0v) notes: 1. guaranteed by design. 12 v 15, v = +5v, operating temperature range (unless otherwise noted) << sl parameters symbol test conditions min typ max units arinc inputs - in1a, in1b, in2a, in2b v(a) - v(b) vih outa = 1 6.5 10 13 volts v(a) - v(b) vil outb = 1 -6.5 -10 -13 volts v(a) - v(b) vnull outa = outb = 0 -2.5 0 2.5 volts (|v(a)| - |v(b)|) / 2 vcm frequency = 80khz 5 volts input resistance - input a to input b ri supply pins floating 30k 50k ohms input resistance - input a or b to gnd rg supply pins floating 19k 25k ohms input capacitance - input a to b ci filter caps disconnected - see note 1 5 10 pf input capacitance - input a or b to gnd cg filter caps disconnected - see note 1 5 10 pf test inputs - testa, testb logic 1 input voltage vih arinc inputs to gnd, ta = 25c 2.7 volts logic 0 input voltage vil arinc inputs to gnd, ta = 25c 0.8 volts logic 1 input current (magnitude) iih vih = 2.7v 5 15 a logic 0 input current iil vil = 0v 0.5 1 a outputs - out1a, out1b, out2a, out2b voltage - sourcing 100a voh ta = 25c 4 volts voltage - sourcing 2.8ma voh full temperature range 3.5 volts voltage - sinking 100a vol ta = 25c 0.08 volts voltage - sinking 2.0ma vol full temperature range 0.8 volts rise time tr cl = 50pf, ta = 25c 40 70 ns fall time tf cl = 50pf, ta = 25c 30 70 ns propagation delay - low to high (arinc) tplh cl = 50pf, ta = 25c and filter caps disconnected 600 ns propagation delay - high to low (arinc) tphl cl = 50pf, ta = 25c and filter caps disconnected 600 ns propagation delay - low to high (testa/b) ttlh cl = 50pf, ta = 25c 50 ns propagation delay - low to high (testa/b) tthl cl = 50pf, ta = 25c 50 ns supply current +vs current idd vs = 15v, ta =25c, testa and testb = 0v 3.7 7 ma +vs current idd vs = 12v, ta =25c, testa and testb = 0v 3 6 ma -vs current iee vs = 15v, ta =25c, testa and testb = 0v 8.7 15 ma -vs current iee vs = 12v, ta =25c, testa and testb = 0v 7.4 14 ma +vl current icc vs = 15v, ta =25c, testa and testb = 0v 9 20 ma +vl current icc vs = 12v, ta =25c, testa and testb = 0v 8.6 18 ma holt integrated circuits 5
additional hi-8482 pin configurations (all 20-pin package configurations) 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 3 - cap2b 2 - testa 1--v 20 - testb 19 - cap1a s in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 +v - 11 out1b - 12 n/c-13 l s 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 3 - cap2b 2 - testa 1--v 20 - testb 19 - cap1a s in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 +v - 11 out1b - 12 n/c-13 l s 20 - testb 19 - cap1a 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 13 - n/c 12 - out1b 11-+v s -v - 1 testa - 2 cap2b - 3 in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 s l 20 - testb 19 - cap1a 18 - in1a 17 - cap1b 16 - in1b 15 - out1a 14 - gnd 13 - n/c 12 - out1b 11-+v s -v - 1 testa - 2 cap2b - 3 in2b - 4 out2b - 5 in2a - 6 cap2a - 7 out2a - 8 +v - 9 n/c-10 s l hi-8482d hi-8482dt 20-pin cerdip hi-8482c hi-8482ct hi-8482cm-01 20-pin ceramic side-brazed dip hi-8482u hi-8482ut 20-pin j-lead cerquad hi-8482s hi-8482st hi-8482sm-01 20-pin ceramic lcc hi-8482 holt integrated circuits 6
hi-8482 ordering information & thermal characteristics hi - 8482 (cerdip & cerquad) xx temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t blank lead finish tin / lead (sn / pb) solder tin / lead (sn / pb) solder 20 pin cerdip (20d) part number ja u 20 pin j-lead cerquad (20u) jc thermal res. d 25c/w 95c/w 28c/w 90c/w package description hi - 8482 (ceramic dip & lcc) xx temperature range flow burn in -40c to +85c no i -55c to +125c -55c to +125c no yes t m part number t m-01 blank lead finish tin / lead (sn / pb) solder gold gold 20 pin ceramic side brazed dip (20c) part number ja s 20 pin ceramic leadless chip carrier (20s) jc thermal res . c 25c/w 85c/w 28c/w 95c/w package description part number f blank lead finish tin / lead (sn / pb) solder 100% matte tin (pb-free, rohs compliant) hi - 8482 (plastic plcc & wide body soic) xx x x 20 pin plastic j-lead plcc (20j) part number ja jc thermal res. j 30c/w 85c/w package description 20 pin plastic small outline (soic) wb (20hw) ps 17c/w 90c/w temperature range flow burn in -40c to +85c no i -40c to +85c no i part number i blank -55c to +125c no t t (8482j only) (8482ps only) (8482j or 8482ps) holt integrated circuits 7
hi-8482 package dimensions 20-pin plastic small outline (soic) - wb (wide body) inches (millimeters) package type: 20hw bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .5035 .0075 (12.789 .191) .4065 .0125 (10.325 .318) .295 .002 (7.493 .051) 0 to 8 .090 .010 (2.286 .254) .0075 .0035 (.191 .089) .018 (.457) typ see detail a detail a .033 .017 (.838 .432) .0105 .0015 (.2667 .0381) .050 (1.27) bsc 20-pin ceramic side-brazed dip inches (millimeters) package type: 20c bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .017 .002 (.432 .051) .100 (2.54) .310 010 (7.874 .254) .125 (3.175) .200 (5.080) 1.000 .010 (25.400 .254) .010 002/ .001 (.254 .051 .025) .300 010 (7.620 .254) .085 .009 (2.159 .229) bsc max min .050 (1.270) typ holt integrated circuits 8
hi-8482 package dimensions 20-pin cerdip inches (millimeters) package type: 20d bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 20-pin plastic plcc inches (millimeters) package type: 20j pin no. 1 ident .045 x 45 .353 .003 (8.966 .076) sq. .017 .004 (.432 .102) .390 .005 (9.906 .127) sq. .173 .008 (4.394 .203) . 310 .020 (7.874 .508 ) .049 x 45 .050 (1.27) bsc see detail a detail a .035 .889 r .010 .001 (.254 .03) .020 (.508) min bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 1.060 max (26.924 max) .005 min (.127 min) .070 max (1.778 max) .288 .005 (7.315 .127) .060 typ (1.524 typ) .015 min (.381 min) .200 max (5.080 max) .125 min (3.175 min) .018 .003 (.457 .760) 0 to 15 .010 .002 (.254 .051) .310 .010 (7.874 .254) .170 max (4.318 max) .100 bsc (2.54) holt integrated circuits 9
hi-8482 package dimensions 20-pin ceramic leadless chip carrier inches (millimeters) package type: 20s bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) pin 1 .020 (.508) .040 x 45 (1.016 x 45) .175 .004 (4.445 .101) .009r .006 (.229r .152) .050 .005 (1.270 .127) .350 .008 (8.890 .203) sq. .080 .020 (2.032 .508) .050 (1.270) .075 .004 (1.905 .101) .025 .003 (.635 .076) pin 1 bsc index 3 plcs 20-pin j-lead cerquad inches (millimeters) package type: 20u bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 2 1 20 19 .335 .010 (8.509 .254) .405 (10.287) sq. .375 .008 (9.525 .203) .019 .003 (.483 .076) .050 bsc (1.270) .040 (1.016) typ .190 (4.826) max max holt integrated circuits 10
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